Typical random accessible semiconductor memories include SRAMs and DRAMs. The SRAM performs a read/write operation at a high speed compared with the DRAM, and requires no refresh operation unlike the DRAM, and therefore the SRAM has an advantage that it can easily be handled and a data holding current in a stand-by state is low, but six transistors are required per memory cell for forming the SRAM, and therefore the SRAM has a disadvantage that its chip size increases and thus the cost is increased, compared with the DRAM.
On the other hand, the memory cell of the DRAM can be formed by one capacitor and one transistor, thus allowing a large capacity memory to be constituted with a small chip size, and the DRAM is cheaper than the SRAM if semiconductor memories having the same memory capacity are formed. However, since the DRAM gives a row address and a column address separately as addresses and thus requires a RAS (row address strobe) signal and a CAS (column address strobe) signal as signals specifying timing of capturing the addresses, and requires a control circuit for refreshing the memory cell on a regular basis, the DRAM has a disadvantage that timing control is complicated and current consumption increases compared with the SRAM.
Currently, the dominating semiconductor memory device employed in portable electronic devices represented by cellular phones and the like is the SRAM. This is because the SRAM is suitable for cellular phones for which it is desired that continuous call time and continuous standby time should be prolonged as much as possible because of the low standby current and low power consumption, the conventional cellular phone does not require a very large capacity semiconductor memory device because it is equipped with only simple features, the SRAM is easily handled in terms of timing control and the like, and so on.
On the one hand, the current cellular phone is equipped with the e-mail send/receive feature and the feature such that a WEB server on the internet is accessed and the contents of a homepage are simplified and displayed, and it can be expected that in the future, the home page and the like on the internet can be freely accessed like the current personal computer and the like. For realizing such features, graphic display for providing a variety of multimedia information to a user will be prerequisite, and it will be required that a large capacity semiconductor memory device should be provided for temporarily storing mass data received from a public network and the like in the cellular phone.
On the other hand, the portable electronic device is required to have a reduced size, a reduced weight and reduced power consumption, and therefore an increase in size, an increase in weight and an increase in power consumption should be avoided while the capacity of the semiconductor memory device is increased. Thus, for the semiconductor memory device mounted on the portable electronic device, the SRAM is preferable if considering ease of handling and power consumption, but the DRAM is preferable in terms of the large capacity. That is, it can be said that a semiconductor memory device having merits of both the SRAM and DRAM is most suitable for the future portable electronic device.
As such a semiconductor memory device, one called “pseudo SRAM” having specifications almost same as the SRAM when seen from outside while using memory cells same as those employed in the DRAM has been proposed (e.g. Japanese Laid-Open Patent Publication No. 61-5495, Japanese Laid-Open Patent Publication No. 62-188096, Japanese Laid-Open Patent Publication No. 63-206994, Japanese Laid-Open Patent Publication No. 4-243087 or Japanese Laid-Open Patent Publication No. 6-36557).
However, the pseudo SRAM requires the refresh operation to be constantly performed for holding data stored in memory cells because the memory cell itself is identical to that of the DRAM. Thus, for example, in the pseudo SRAM described in Japanese Laid-Open Patent Publication No. 4-243087 or Japanese Laid-Open Patent Publication No. 63-206994, if a read or write request is made from outside, refresh is first performed, and then read or write of memory cells matching the read request or write request is performed. Thus, there is a problem such that timing of the operation of read or write of memory cells is delayed by time required for the refresh operation.
Furthermore, the pseudo SRAM described in the above Japanese Laid-Open Patent Publication No. 61-5495, Japanese Laid-Open Patent Publication No. 62-188096 or Japanese Laid-Open Patent Publication No. 6-36557 comprises a timer for refresh therein, wherein a refresh start request is made at the time when a predetermined time period elapses, and refresh is performed after completion of read, and thus the time delay described above never occurs for the reading operation, but there is no description as to timing in which a write enable signal determining write timing is given, and the following problem arises in the case of the write operation.
That is, if the pseudo SRAM is to be operated in specifications same as those of the general purpose SRAM, the write enable signal and write data are given asynchronously with a change of an address, and therefore the operation of write in a memory cannot be actually started until the enable signal and write data are both determined even if the write address is determined. That is, vacant time during which no operation is performed is spent until the write enable signal and write data are determined, and write and refresh are performed in sequence only after the write enable signal and write data are determined. Thus, there is a disadvantage that a memory cycle is prolonged by the vacant time, compared with the configuration in which refresh is performed and then write is performed.
In terms of solving the problem such that this refresh slows a normal read/write access, the applicant proposed, in Japanese Patent Application No. 2001-105837 (Japanese Laid-Open Patent Publication No. 2001-357671, International Patent Application WO01/78079A1), a semiconductor memory device comprising a memory cell array constituted by memory cells requiring refresh, in which a write request and write data are asynchronously given to an access address, wherein a refresh operation is performed after read or write to the access address is performed, and at a time point after a memory cycle in which the above described write request is given, write using the above described access address and the above described write data given in the memory cycle is performed in late write.
FIG. 1 is a block diagram showing an example of the semiconductor memory device proposed in the Japanese Patent Application 2001-105837, and FIG. 2 is a timing chart showing the late write operation and refresh operation of the semiconductor memory device.
In FIGS. 1 and 2, an address Add is an access address supplied from outside of the semiconductor memory device. The address Add includes a row address and a column address in accordance with an arrangement of a memory cell array 107 in a matrix form. An address buffer 101 buffers and outputs the address Add. A latch 102 outputs directly as an internal address LC-ADD an address supplied from the address buffer 101 as long as a latch control signal LC is at an “L” level (during a time period after the latch control signal LC falls until it rises again). Furthermore, the latch 102 captures the address supplied from the address buffer 101 at the rise of the latch control signal LC, holds the address as long as the latch control signal LC is at a “H” level, and outputs the held address as an internal address LC-ADD.
Control signals LW1 and LW2 supplied from an R/W control circuit 114 to register circuits 103 and 112 are signals for control of the late write signal. The control signals are both set at the “H” level when late write is performed and set at the “L” level otherwise. The register circuit 103 includes therein a register (hereinafter referred to as address register) for holding an access address identical in bit width to the address Add. Thus, if the control signal LW1 is at the “L” level, the register circuit 103 outputs the inputted internal address LC-ADD directly as an internal address L-ADD. On the other hand, if the control signal LW1 id at the “H” level, the register circuit 103 outputs an address held in the address register, other than the internal address LC-ADD, as the internal address L-ADD.
Furthermore, the register circuit 103 captures the internal address LC-ADD in the internal register for next late write at a fall edge of the control signal LW1. Further, the register circuit 103 comprises a comparator comparing the inputted internal address LC-ADD with the address held by the address register on a bit-by-bit basis, and the comparator outputs the “H” level as a hit signal HITS if the former is consistent with the latter in all bits, and outputs the “L” level if they are not consistent with each other in one or more bits. The hit signal HITS is used in a bypass operation for maintaining data coherency seen from outside of the semiconductor memory device.
In late write employed in the semiconductor memory device, write in memory cells is actually performed in the memory cycle after the memory cycle in which the write request is made. That is, in the memory cycle in which the write request is made, the write address and write data are temporarily captured in the address register of the register circuit 103 and a data register of the register circuit 112. Write in the memory cell array 107 is then performed based on the address and data captured in the memory cycle in which the write request is inputted. Thus, if the read request is made for the address for which the write request has been made by the time when write in the memory cell array 107 is actually performed, data is not written in the memory array 107 yet at this time, but exists only in the register circuit 112.
Accordingly, if read from the memory cell array 107 is performed, old data before write is outputted to outside of the semiconductor memory device. In this case, the memory cell array 107 is bypassed and data stored in the register circuit 112 is outputted. For detecting this situation, the internal address LC-ADD is checked against the address resister in the register circuit 103 to detect by the comparator in the register circuit 103 that the read request has been inputted from outside for the address not written yet in the memory cell array 107. An ATD (address transition detector) circuit 104 detects whether the internal address LC-ADD is changed if a chip select signal/CS (symbol “/” means negative logic) is effective (at “L” level).
If a change is observed in one or more bits of the internal address LC-ADD, the ATD circuit 104 generates a positive one shot pulse as an address transition detection signal after a time period corresponding to an address skew period elapses after the time point at which the change is detected. The chip select signal/CS is a select signal enabled when the semiconductor memory device is accessed. In the ATD circuit 104, if bits of the address are changed or the chip select signal/CS is enabled, pulses are generated, and the pulses are combined to generate a one shot pulse. Thus, even if the address ADD has a skew, there is no possibility that a plurality of address transition detection signals are generated. Therefore, there arises no situation in which write in a plurality of memory cells is performed, or read from a plurality of memory cells is performed at a time, resulting in corruption of data in the memory cell.
Furthermore, if the skew is large, the address skew time period is prolonged, generation of the one shot pulse as the address transition detection signal ATD is accordingly delayed, and access time increases but in specifications of the general purpose SRAM, access time has a value based on the time point at which the address Add is determined, and therefore only access time from a bit changed most recently, of bits of the address Add, should be insured, and no operation delay occurs even if access is started after the address skew period elapses. Read or write to the address Add is started at the time when the one shot pulse of the address transition detection signal ATD rises, and then refresh is started at the time when the one shot pulse falls. Accordingly, the pulse width of the one shot pulse of the address transition detection signal ATD is set to at least a time period required for completion of read or write.
Furthermore, the duration of the address skew is matched with the maximum value of skews existing between bits of the address Add and chip select signals/SC, or set to a value slightly larger than the maximum value of the skew for leaving a margin. Because the skew occurs for the reason described above, the maximum value of the skew is estimated and determined in advance based on characteristics of the entire system to which the semiconductor memory device is applied. The refresh control circuit 105 includes therein an address counter (refresh counter) and a refresh timer. The refresh control circuit 105 uses the above counter and timer, the address transition detection signal ATD and the write enable signal/WE to control refresh in the semiconductor memory device, whereby the refresh address and refresh timing are automatically generated in the semiconductor memory device, and refresh similar to self-refresh in the general purpose DRAM is realized.
The address counter sequentially generates refresh address addresses R-ADD for refreshing DRAM memory cells. The refresh address R-ADD has a bit width same as that of the row address included in the address Add. The refresh timer counts time passing after the access request is made from outside of the semiconductor memory device most recently, and it causes self refresh to be started in the semiconductor memory device when the time exceeds a predetermined refresh time period. Accordingly, the refresh timer is configured to be reset and restart counting time each time the address transition detection signal ATD is enabled. A multiplexer (MUX) 106 selects a row address included in the internal address L-ADD and outputs the same as an address M-ADD if the address transition detection signal AID is at the “H” level and the refresh control signal REFB is at the “H” level, according to the levels of the address transition detection signal ATD and the refresh control signal REFB.
On the other hand, if the address transition detection signal ATD is at the “L” level or the refresh control signal REFB is at the “L” level, the refresh address R-ADD is selected and outputted as the address M-ADD. The memory cell array 107 is a memory cell array similar to that of the general purpose DRAM, wherein word lines and bit lines (or bit line pair) run in row and column directions, respectively, and memory cells each constituted by one transistor and one capacitor like the DRAM are arranged at intersections of the word lines and the bit lines in a matrix form. When a row enable signal RE is at the “H” level, a row decoder 108 decodes the address M-ADD to activate a word line designated by the address M-ADD. When the row enable signal RE is at the “L” level, the row decoder 108 activates none of word lines.
When a column enable signal CE is at the “H” level, a column decoder 109 decodes the column address included in the internal address L-ADD, and generates a column selection signal for selecting a bit line designated by the internal address L-ADD. When the column enable signal/CE is at the “L” level, the column decoder 109 generates no column selection signal corresponding to any of bit lines. A sense amp/precharge circuit 110 is comprised of a sense amp, a column switch and a precharge circuit. The column switch establishes connection between the sense amp designated by the column selection signal outputted by the column decoder 109 and a bus WRB. The sense amp sense-amplifies the potential of the bit line to which the memory cell specified by the address Add is connected, and outputs the same to the bus WRB, or writes write data supplied to the bus WRB in the memory cell through the bit line when a sense amp enable signal SE is at the “H” level.
The precharge circuit pre-charges the potential of the bit line into a predetermined potential (e.g. ½ of power supply potential) when a precharge enable signal PE is at the “H” level. A hit control circuit 111 and a register circuit 112 perform the late write operation in cooperation with the above described register circuit 103. Among them, the hit control signal 111 captures the hit signal HITS at the rise of the address transition detection signal ATD, and sends the signal to the register circuit 112 as the hit enable signal HE. The value of the address Add is not determined within the address skew period, and therefore the hit control circuit 111 captures the hit signal HITS at the time when the address Add is determined. The register circuit 112 includes therein a data register having a bit width same as that of data exchanged on the bus WRB. The register circuit 112 captures write data supplied onto the bus WRB from outside through an I/O buffer 113 into the data register with a fall edge of the control signal LW2 as a trigger.
That is, if a write request is made, write data given in the memory cycle is temporarily captured in the data register, and the captured write data is written in the memory cell array 107 in the memory cycle in which a next write request is made. That is, if the control signal LW2 is at the “H” level, the register circuit 112 outputs the write data given in response to the immediately preceding write request from the data register onto the bus WRB. On the other hand, in the case of the read operation in which the control signal LW2 is at the “L” level, the register circuit 112 performs an operation varying depending on the levels of the hit enable signal HE. That is, if the hit enable signal HE is at the “L” level indicating a miss hit, the register circuit 112 outputs read data on the bus WRB directly onto a bus WRBX.
On the other hand, if the hit enable signal HE is at the “H” level indicating a hit, the register circuit 112 sends write data not written yet in the memory cell array 107 onto the bus WRBX from the data register in the register circuit 112. In this case, data of the memory cell array 107 read onto the bus WRB through the sense amp/precharge circuit 10 is not used. The I/O (input/output) buffer 113 buffers read data on the bus WRBX with an output buffer and outputs the same from a bus I/O to outside of the semiconductor memory device if a control signal CWO from the R/W control circuit 114 is at the “H” level, and it buffers write data supplied from outside of the semiconductor memory device to the bus I/O with an input buffer with the output buffer in a floating state, and sends the same onto the bus WRBX if the control signal CWO is the “L” level. That is, read is performed if the control signal CWO is at the “H” level, and write is performed if the control signal CWO is at the “L” level.
The R/W (read/write) control circuit 114 generates the control signal CWO and control signals LW1 and LW2 based on the chip select signal/CS, the write enable signal/WE and an output enable signal/OE. Late write is performed in the semiconductor memory device but in specifications when seen from outside of the semiconductor memory device, write (capturing) of data is started at the fall edge of the write enable signal/WE, data is determined at the rise edge of the write enable signal/WE, and write (capturing) is completed. A latch control circuit 115 generates the above latch control signal LC determining latch timing of the address Add based on the address transition detection signal ATD and the sense amp enable signal SE. The latch control signal LC is at the “H” level during a period after the rise edge of the address transition detection signal ATD until the fall edge of the sense amp enable signal SE generated during the refresh operation (the address transition detection signal ATD is at the “L” level).
Consequently, even if the address Add changes after the address transition detection signal ATD rises, the latch 102 continuously holds the value of the internal address LC-ADD until the latch control signal LC falls. A row control circuit 116 generates the row enable signal RE, the sense amp enable signal SE, the precharge enable signal PE and a column control signal CC based on refresh control signals REFA and REFB, the address transition detection signal ATD and the write enable signal/WE. The column control circuit 117 generates a column enable signal/CE based on the column control signal/CC. That is, at the time of read or write, the row control circuit 116 generates a positive one shot pulse in the row enable signal RE with the rise of the one shot pulse of the address transition detection signal ATD as a trigger.
Furthermore, if the refresh control signal REFA is at the “H” level, the row control circuit 116 generates a positive one shot pulse, which is required for the refresh operation, in the row enable signal RE with the fall edge of the one shot pulse of the address transition detection signal ATD as a trigger. Moreover, the row control circuit 116 outputs as the row enable signal RE a positive one shot pulse obtained by reversing a negative one shot pulse that is supplied to the refresh control signal REFB. Furthermore, the row control circuit 116 delays the row enable signal RE to generate a positive one shot pulse in the sense amp enable signal SE, and generates a positive one shot pulse in the precharge enable signal PE with the fall of the one shot pulse generated in the row enable signal RE as a trigger. The sense amp enable signal SE and precharge enable signal PE are generated regardless of normal write/read or refresh.
Furthermore, the row control circuit 116 delays the row enable signal RE to output the column control signal CC. The column control signal CC is not generated in the case of refresh, and therefore the column enable signal CE generated from the column control signal CC is also generated only in the case of normal write/read, and is not generated in the case of refresh. A column control circuit 117 further delays the control signal CC, and outputs the control signal CC as the column enable signal/CE. The width of the one shot pulse of the row enable signal RE determines time periods of late write, read and refresh, respectively, and therefore a pulse width necessary and sufficient for these operations is set.
The refresh control signal REFA outputted from the refresh control circuit 105 is a signal for controlling whether or not refresh is to be performed in association with an access request from outside of the semiconductor memory device, and if the signal is at the “H” level, a one shot pulse is generated in the row enable signal RE to start refresh at the fall of the address transition detection signal ATD generated according to the access request. On the other hand, if the signal is at the “L” level, no one shot pulse is generated in the row enable signal RE even if a one shot pulse is generated in the address transition detection signal ATD. In this semiconductor memory device, if the refresh operation associated with read or write continues, refresh is continuously performed in association with the memory cycles to refresh all memory cells.
At the time when all memory cells are refreshed, a state is created on a temporary basis in which refresh no longer occurs. Thereafter, when the limit of capability of holding data of memory cells (cell hold limit) is approached, this is detected, and a transition is made again to a state in which refresh is performed continuously in continuous memory cycles. As a factor of fall of the refresh control signal REFA, there is a case where refresh of one cycle is completed according to refresh associated with an access request from outside, but some time still remains until refresh of the next cycle is started, or a case where self-refresh is started, and therefore refresh associated with an access request from outside is required only after the self-refresh is completed. For generating the refresh control signal REFA, there is a method in which a latch circuit holding the refresh control signal REFA is provided in the refresh control circuit 105, and the set/reset of this latch circuit is controlled by the output signal of the refresh timer and the address transition detection signal ATD, or the like.
Specifically, timing just before the cell hold limit requiring the refresh operation is generated with the refresh timer and based on the output signal thereof, a set signal of the latch circuit is generated in the refresh control circuit 105 to set the latch circuit, and the “H” level is outputted to the refresh control signal REFA. Timing for generating the set signal is determined on the basis of the maximum value of cycle time. Then, the row control circuit 116 performs the refresh operation of memory cells by the word line unit using as a trigger the refresh control signal REFB generated based on the address transition detection signal ATD or refresh control signal REFA. When the refresh operation for all memory cells is performed, a reset signal of the latch circuit is generated in the refresh control circuit 105 to reset the latch circuit, and the “L” level is outputted to the refresh control signal REFA.
The reset of the latch circuit is performed in synchronization with a time when the refresh operation is completed in a refresh cycle in which the last word line is refreshed. Alternatively, the row control circuit 116 is caused to generate a refresh operation completion signal when the refresh operation is completed, and the latch circuit is reset when the refresh control circuit 105 receives the refresh operation completion signal in the refresh cycle for the last word line. On the other hand, the refresh control signal REFB is a signal for self-refresh. By giving a negative one shot pulse to the refresh control signal REFB, a one shot pulse can be forcefully generated in the row enable signal RE to start refresh.
For generating the refresh control signal REFB, it can be considered that a delay circuit delaying the refresh control signal REFA and a pulse generator circuit generating a negative one shot pulse are provided in the refresh control circuit 105, and timing for generating the negative one shot pulse from the pulse generator circuit is controlled by the refresh control signal REFA delayed by the delay circuit and the address transition detection signal ATD, and the like. Usually, the refresh control signal REFB is at the “H” level. If the refresh control signal REFA is caused to rise into the “H” level in this state, the rise of the refresh control signal REFA is delayed by a predetermined time period by the delay circuit, and if during the delay, no address transition detection signal ATD is generated, the pulse generator circuit is activated at the rise of the delayed refresh control signal REFA, and the refresh control signal REFB is caused to output a negative one shot pulse.
The above delay by a predetermined time period is set for making a measurement until time of a limit required for refresh of memory cells because a trigger for generating the address transition detection signal ATD is not given from outside. Furthermore, if a write request is given only after the semiconductor memory device is started up, only the write address and write data are captured, and late write onto the memory cell array 107 is not performed in a memory cycle in which the write request is made because no immediate preceding write exists. For realizing this, a flag is provided in the row control circuit 116, with the flag indicating whether the write enable signal/WE has been enabled at least one time in a state with the chip select signal/CS enabled. The row control circuit 116 initializes the flag into OFF at the time of startup of the semiconductor memory device is activated, and turns the flag ON at the time when a first write request is made.
Furthermore, when the write request is made (write enable signal/WE=“L” level and chip select signal/CS=“L” level), the row control circuit 116 generates a one shot pulse in the row enable signal RE only if the flag is ON. Consequently, the row control circuit 116 and the column control circuit 17 generate the control signal CC, the sense amp enable signal SE, the column enable signal/CE and the precharge enable signal PE which are required for write.
Furthermore, in FIG. 1, a boost power source 118 is a power source supplying to the row decoder 108 a up-convert potential applied to the word line in the memory cell array 107, a substrate voltage generator circuit 119 is a circuit generating a substrate voltage applied to a well on which memory cells of the memory cell array 107 are formed, or a semiconductor substrate, and a reference voltage generator circuit 120 is a circuit generating a reference voltage (e.g. ½ of power source potential) used by the memory cell array 107, the sense amp in the sense amp/precharge circuit 110, and the precharge circuit/equalize circuit. The refresh control circuit 105, the boost power source 118, the substrate voltage generator circuit 119 and the reference voltage generator circuit 120 are supplied with power down control signals PD.
The power down control signal PD is a signal for designating from outside of the semiconductor memory device a mode for setting the semiconductor memory device at a power down state (standby state). The refresh control circuit 105, the boost power source 118, the substrate voltage generator circuit 119 and the reference voltage generator circuit 120 are configured to control power supply to them, respectively, according to the power down control signal PD. For the semiconductor memory device shown in the figure, the memory cell itself is similar to that of the DRAM, and therefore power supply to circuit portions in the semiconductor memory device cannot be simply stopped in the standby state unlike the SRAM. Even in the standby state, power should be continuously supplied to circuits required for the refresh operation for holding data of the memory cell.
Thus, the semiconductor memory device is provided with several modes in the standby state to ensure compatibility with the SRAM as much as possible, and also provided with modes that would not exist in existing semiconductor memories. Specifically, three types of standby modes are provided, and standby mode 1 is a power supply mode equivalent to that of the usual DRAM, and takes the highest current consumption in the three types of standby modes. In this case, however, power is still supplied to all circuits required for refresh of the memory cell. Thus, data of the memory cell immediately before transition to the standby state is held, and also time taken until transition of the semiconductor memory device from the standby state to the active state is the shortest in the three types of standby modes.
Standby mode 2 is a mode for stopping power supply to the refresh control circuit 105, wherein no power is supplied to circuits required for refresh, and therefore data of the memory cell cannot be held in the standby state, but current consumption can be reduced accordingly compared with standby mode 1. This mode results from a shift from the established concept that data is held in the standby state, and if a transition is made from the standby state to the active state, write can be performed over the entire memory cell array.
Standby mode 3 is a mode for stopping power supply to the refresh control circuit 105, the boost power source 118, the substrate voltage generator circuit 119 and the reference voltage generator circuit 120, wherein as the boost voltage, substrate voltage, and reference voltage are required to atartup, time until transition from the standby state to the active state is the longest in the three types of standby modes, but current consumption in the standby mode can be the lowest. Standby mode 2 and standby mode 3 are modes suitable for use of the semiconductor memory device as a buffer. Furthermore, in any case of standby modes 1 to 3, power is supplied to required circuits for circuits other than the four types of circuits described above.
Operations of the above prior art will now be described with reference to FIGS. 1 and 2. As described above, it is exceptional in that for first write after startup of the semiconductor memory device, the operation is different from operations of second and subsequent write. FIG. 2 shows second and subsequent write operations assuming that at least first write has been performed. That is, assume that a request of write of data “Qx” to an address “Ax” was made in the previous memory cycle. Consequently, in the memory cycle, the address “Ax” is captured in the address register of the register circuit 103, and data “Qx” is captured in the data register of the register circuit 112.
FIG. 2 shows operation timing where write to the address “An” and read from the address “An+1” are performed consecutively. Furthermore, the value of the refresh address R-ADD is “R1−1” before write. Furthermore, the address “An−1” is an address given in the immediately preceding memory cycle. If the write request was made in the immediately preceding memory cycle, the address “An” equals the address “Ax” and otherwise, there was at least one read request between the immediately preceding write request and the request of write to the address “An”.
First, in the case of the memory cycle for write, at the time t1, the address Add starts to change from the value “An−1” kept hitherto to “An”. At this time, the latch control signal LC is at the “L” level, and the control signal LW1 is at the “L” level. Accordingly, the address Add is buffered by the address buffer 101, and passes through the latch 102 to change into an internal address LC-ADD, and the internal address LC-ADD passes through the register circuit 103 to change into an internal address L-ADD. The ATD circuit 104 detects that the address Add starts to change from the change of the internal address LC-ADD. Furthermore, the address skew period (equivalent to TSKEW) at this time, and therefore the value of the address Add is not necessarily determined at this time same as in the case of the general-purpose SRAM.
Therefore, the address Add cannot be captured in the latch 102 at time t1 and thereafter, the address Add is held in the latch 102 at the time when the value of the address Add is determined as “An” after elapse of time TSKEW. Furthermore, a negative pulse is inputted to the write enable signal/WE at, for example, time t2 within the address skew period. The R/W control circuit 114 turns the control signal CWO into the “L” level in response to the fall of the write enable signal/WE, and also turns both control signals LW1 and LW2 into the “H” level. As a result, the I/O buffer 113 sends write data on the bus I/O onto the bus WRBX. The vale of write data is not necessarily determined at this time. The register circuit 103 outputs as the internal address L-ADD the address “Ax” held in the address register, and the register circuit 112 outputs onto the bus WRB the data “Qx” held in the data register.
At time t3, the value of the address Add is determined as “An”. Furthermore, at time t3, time TSKEW elapses after the time at which the address Add (=internal address LC-ADD) starts to change, and therefore the ATD circuit 104 generates a positive one shot pulse in the address transition detection signal ATD at subsequent time t4. In response to rise of the address transition detection signal ATD, the refresh circuit 105 increments the value of the refresh address R-ADD by “1” to update the value to “R1” for the refresh operation that is performed subsequently to write. The late write operation is started at the rise of the address transition detection signal ATD. That is, the multiplexer 106 selects the internal address L-ADD side in response to the rise of the address transition detection signal ATD.
At this time, the register circuit 103 outputs as the internal address L-ADD the address “Ax” held by the address register, and the multiplexer 106 outputs this value to the row decoder 108 as the address M-ADD. Furthermore, in the same way, the row control circuit 116 generates a positive one shot pulse in the row enable signal RE in response to the rise of the address transition detection signal ATD. Consequently, the row decoder 108 activates a word line corresponding to the address “Ax”. Then, in response to the one shot pulse of the row enable signal RE, the row control circuit 116 generates a positive one shot pulse in the sense amp enable signal SE, and also generates a positive one shot pulse in the control signal CC and outputs the same to the column control circuit 117. Consequently, the column control circuit 117 generates a positive one shot pulse in the column enable signal/CE.
When the column enable signal CE is turned into the “H” level in this way, the column decoder 109 decodes a row address included in the internal address L-ADD (=address “Ax”), and generates a positive one shot pulse in a column selection signal corresponding to the row address. As a result, of sense amps in the sense amp/precharge circuit 110, a sense amp corresponding to the above row address is selected and connected to the bus WRB. As a result thereof, write of data “Qx” in a memory cell corresponding to the address “Ax” through the sense amp in the sense amp/precharge circuit 110 is started at time t4. Thereafter, at time 5, data “Qn” being write data to the address “An” is supplied, and the data is carried on the bus I/O and sent onto the bus WRBX through the I/O buffer 113.
At this time, the bus WRBX is not connected to the bus WRB, the data “Qn” is not involved in write in the memory cell array 107. Thereafter, the row control circuit 116 causes the one shot pulse of the row enable signal RE to fall for completing the write operation of the row control circuit 116. Thereupon, the row decoder 108 deactivates a write word line corresponding to the address “Ax”. Then, the row control circuit 116 causes the sense amp enable signal SE to rise to complete the write operation through the sense amp in the sense amp/precharge circuit 110. Then, the row control circuit 116 causes the control signal CC to fall, and the column control circuit 117 responding to the fall causes the column enable signal CE to fall. As a result, the column decoder 109 disables the column selection signal to separate the sense amp in the selected sense amp/precharge circuit 110 from the bus WRB.
Then, the row control circuit 116 causes the precharge enable signal PE to rise, whereby the precharge circuit in the sense amp/precharge circuit 110 pre-charges bit lines in preparation for the next access. Then, after elapse of a time period required for the precharge operation, the row control circuit 116 causes the precharge enable signal PE to fall to complete the operation of precharge of bit lines by the precharge circuit in the sense amp/precharge circuit 110. Then, when the address transition detection signal ATD falls at time t6, the refresh operation is started. That is, the address transition detection signal ATD is turned into the “L” level, whereby the multiplexer 106 selects the refresh address R-ADD, and outputs “R1” as the address M-ADD.
Furthermore, in response to the fall of the address transition detection signal ATD, the row control circuit 116 generates a positive one shot pulse in the row enable signal RE. Consequently, the row decoder 108 activates a word line corresponding to the value of the address M-ADD “R1”. As a result, in the memory cell array 107, held data of the memory cell connected to the refresh word line appears as a potential on the bit line. Thereafter, when the row control circuit 116 generates a positive one shot pulse in the sense amp enable signal SE, the sense amp in the sense amp/precharge circuit 110 is activated, and refresh of each memory cell connected to the refresh word line is started. Furthermore, the refresh operation itself is similar to the operation performed in the DRAM.
If the write enable signal/WE is caused to rise at, for example, time t7 in the middle of performing refresh in this way, the R/W control signal 114 causes both control signals LW1 and LW2 to fall. In response to the fall of the control signal LW1, the register circuit 103 captures the value of the internal address LC-ADD “An” in the address register at time t8. Furthermore, in response to the fall of the control signal LW2, the register circuit 112 captures data “Qn” on the bus WRBX into the data register at time t8. The addresses “An” and “Qn” captured in the registers will be used for the late write operation in the memory cycle at the time when the next write request is made. Thereafter, at time t9, the memory cycle for write is completed to make a transition to the memory cycle for read.
At this time, the refresh operation associated with late write is consecutively performed. When a time period required for refresh elapses after start of refresh (time t6), the row control circuit 116 causes the row enable signal RE to fall for completing the refresh operation. Consequently, the row decoder 108 deactivates the fresh word line. Then, the row control circuit 116 causes the sense amp enable signal SE to fall to deactivate sense amps in the sense amp/precharge circuit 110 which have finished refresh. At this time, the latch control circuit 115 causes the latch control signal LC to fall in response to the fall of the sense amp enable signal SE. In the process of refresh, it is not necessary to output data of the memory cell to outside of the semiconductor memory device, and therefore no one shot pulse is generated in the column enable signal CE even if a one shot pulse is generated in the row enable signal RE. Thus, the column decoder 109 keeps the column selection signal in an inactive state.
When the refresh operation is completed as described above, the row control circuit 116 generates a one shot pulse in the precharge enable signal PE to pre-charge the bit line in the same manner as when write is completed. The operation described hitherto is performed by time t10 (when time TSKEW elapses after time of start of the read cycle subsequent to the write cycle) at the latest. In this example, by preventing generation of the one shot pulse of the address transition detection signal ATD as long as the address Add is undetermined, control is performed so that the write or read operation is not started until the address skew period expires, and therefore no problem arises even if the refresh operation is postponed to the time of completion of the address skew period of the next memory cycle. Furthermore, in accordance with this control, the internal address L-ADD used in the write/read address holds the value of the immediately preceding memory cycle during the address skew period.
In FIG. 2, the time t1 to t9 (time t3 to t10 for actual operations) corresponds to one memory cycle, and the cycle time is denoted by “Tcyc”. Furthermore, the time t7 to t9 corresponds to the recovery time TWR described above. In the operation shown in FIG. 2, however, it is not necessary to reserve the recovery time TWR because the precharge operation after late write is completed before the refresh operation. For example, the write enable signal/WE may rise at time t9 and in this case, the recovery time TWR is zero.
Then, in the case of the memory cycle for read, the value of the address Add starts to change from “An” at time t9. In this case, since the address skew period continues until time t10, the address Add is not captured in the latch 102 until the address is determined as “An+1”. Furthermore, if a read request is made, the write enable signal/WE is never caused to fall during the address skew period and instead, the output enable signal/OE is enabled. Thus, the R/W control circuit 114 turns the control signal CWO into the “H” level in preparation for read from the memory cell, and also keeps both the control signals LW1 and LW2 at the “L” level. Consequently, the I/O buffer 113 sends data on the bus WRBX to the bus I/O.
At this time, address skew period still continues, the hit control signal HE is still in the immediately preceding memory cycle, and thus whether data on data WRB is read onto the bus WRBX, or data held in the data register is read is not determined. When the address skew time expires and time t10 is reached, the values of the address Add and the internal address LC-ADD are determined at “An+1”. At this time, the control signal LW1 is at the “L” level, and therefore the value of the internal address LC-ADD is outputted directly as the internal address L-ADD. Furthermore, since the value of the internal address LC-ADD “An+1” is not equal to the address “An” held in the address register, the register circuit 103 outputs the “L” level as the hit signal HITS. At time t11, the ATD circuit 104 generates a positive one shot pulse in the address transition detection signal ATD, whereby the read operation is started.
The refresh control circuit 105 updates the value of the refresh address R-ADD from “R1” to “R1+1”. Furthermore, the hit control circuit 111 captures the hit signal HITS at time t11, and outputs the “L” level as the hit enable signal HE. Consequently, the register circuit 112 connects the bus WRB and the bus WRBX, and the sense result by the sense amp in the sense amp/precharge circuit 110 can be outputted to outside of the semiconductor memory device through the I/O buffer 113 and the bus I/O. The multiplexer 106 selects the internal address L-ADD and outputs the address “An+1” to the row decoder 108 as the address M-ADD. At the same time, the row control circuit 116 generates a positive one shot pulse in the row enable signal RE, and the row decoder 108 activates a word line corresponding to the address “An+1”.
As a result, held data of the memory cell connected to the read word line is read as a potential on the bit line. Then, the row control circuit 116 generates positive one shot pulses in the sense amp enable signal SE and the control signal CC, respectively. Then, the column control circuit 117 generates a positive one shot pulse in the column enable signal/CE, and the column decoder 109 activates a column selection signal corresponding to the row address in the address “An+1”, and connects a sense amp corresponding to the column selection signal to the bus WRB. This sense amp senses data of each memory cell connected to the read word line to amplify the same to the level of “0”/“1”. As a result, at time t13, data “Qn+1” stored in the address “An+1” appears on the bus WRB, and is read from the bus I/O to outside through the register circuit 112, the bus WRBX and the I/O buffer 113.
Thereafter, for completing the read operation, the row control circuit 116 causes the row enable signal RE to rise. Then, in the same manner as in write, a read word line corresponding to the address “An+1” is deactivated, and the sense amp enable signal SE goes into the “L” level so that the sense amp in the sense amp/precharge circuit 110 completes the sense operation. Furthermore, the column control circuit 117 turns the column enable signal CE into the “L” level to separate the sense amp from the bus WRB. Then, the row control circuit 116 generates a one shot pulse in the precharge enable signal PE to pre-charge the bit line. At time t12, the address transition detection signal ATD falls, and the refresh operation associated with read is started.
In this case, the operation performed at time t12 to t15 is same as refresh associated with write except that “R1+1” is used as the refresh address R-ADD instead of “R1”. When time t14 is reached during the refresh operation, the memory cycle for read ends and a new memory cycle subsequent thereto is started, and the refresh operation is completed in the new memory cycle until the address skew period expires. Furthermore, the time t9 to t14 (time t10 to t15 for actual operations) also corresponds to one memory cycle, and the cycle time is denoted by “Tcyc”. In FIG. 2, if the read address is not “An+1” but “An”, write data “Qn” to the address “An” is not reflected yet in the memory cell array 107. Accordingly, a bypass operation described below is performed.
In this case, at time t10 shown FIG. 2, the value of the address Add is determined as “An”, and this value “An” is outputted to the internal address LC-ADD as well. At this time, the address register in the register circuit 103 holds “An”, and therefore the register circuit 103 outputs the “H” level as the hit signal HITS. Thereafter, at time t11 when the address transition detection signal ATD rises, the hit control circuit 111 captures the hit signal HITS, and outputs the “H” level as the hit enable signal HE. Because of the read operation in this case, the R/W control circuit 114 outputs the “L” level as the control signal LW2. Thus, the register circuit 112 outputs data “Qn” held in the data register onto the bus WRBX.
Thereafter, as in the case where the read address is “An+1”, data stored in the address “An” is read from the memory cell array 107 and at time t13, the data is read onto the bus WRB. However, since this data is old data before write, it is not used as read data but discarded. Instead, data “Qn” outputted on the bus WRBX is outputted to outside of the semiconductor memory device through the I/O buffer 113 and the bus I/O. Furthermore, if the bypass operation is performed, read from the memory cell array 107 is not required, and it is therefore possible to reduce current consumption without starting the read operation.
In this case, the hit enable signal HE is also supplied to the row control circuit 116. If a read request is made, and the hit enable signal HE is at the “H” level in timing of rise of the address transition detection signal ATD, the row control circuit 116 and the column control circuit 117 perform control so as not to generate the row enable signal RE and signals chronologically generated from the signal (sense amp enable signal SE, control signal CC, column enable signal/CE, column selection signal, precharge enable signal PE). As described above, in this semiconductor memory device, the write enable signal/WE associated with the write request is caused to rise within the address skew period, and therefore whether the access is write or read is determined at the time when the address is determined.
Moreover, because late write is performed, both the write address and write data are already determined before the address skew period, thus making it possible to start the write operation or read operation immediately at the time when whether the access request is write or read is determined. Furthermore, it is not necessary to reserve recovery time TWR. Thus, time required for write or read is the shortest, thus making it possible to reduce the duration of one memory cycle (time t3 to t10 or time t10 to t15) to a minimum. Furthermore, since refresh is performed after write or read is performed, the speed of access can be enhanced by an amount equivalent to time required for performing refresh compared with the case where read or write is performed after refresh.
In this way, in the method of performing write in the memory cell by late write, if a write request is made, it is not necessary to wait until write data for the write request is determined, and the operation of write in the memory cell corresponding to the previous write request and the refresh operation subsequent thereto, and capturing of next write data can be performed at the same time. Thus, write time does not depend on when write data is determined, write time and read time can be equally fixed, and the refresh operation can be well performed within a predetermined memory cycle after write or read is performed.
In the prior art described above, owing to write by late write, the duration of the memory cycle for write can be reduced to a minimum, which is equivalent to the duration of the memory cycle for read, and therefore the refresh operation can be performed in each write cycle even in a state in which the write cycle is continued, but the refresh operation associated with each memory cycle is started with a trigger signal generated after elapse of a predetermined time period after the ATD circuit 104 detects an address transition outputted from the address latch circuit 102, and therefore a situation may arise in which the refresh operation is not started if no memory access is made for a long time.
For avoiding such a situation, a refresh timer is included in the refresh control circuit 105 in the prior art described above. The refresh timer clocks time passing after an access request is most recently made from outside of the semiconductor memory device and if it exceeds predetermined refresh time, self-refresh is started in the semiconductor memory device. Thus, the refresh timer is configured to be reset and restart clocking each time when the address transition detection signal ATD is enabled.
That is, in the above prior art, refresh is performed in association with each memory cycle and therefore if memory accesses are successively made, the memory refresh operation may be performed more than necessary, resulting in wasted power consumption. Furthermore, as a memory refresh unit, two units, i.e. a refresh unit associated with each memory cycle and a refresh apparatus constituted by a refresh timer are provided, and the configuration for refresh is duplicated, thus causing an increase in cost.